The invention relates to a data processing arrangement comprising a plurality of processors which share a collective memory. The invention may be applied in, for example, an integrated circuit capable of decoding an MPEG data stream.
The document WO 95/32578 describes an MPEG decoder. The MPEG decoder has an external DRAM memory. A control unit controls the external DRAM memory and an internal bidirectional bus. All the data transfers between the external DRAM memory and the various internal units proceed via this bus.
It is an object of the invention is to enable implementations to be realized at comparatively low cost, particularly implementations for high-speed processing.
The invention takes into account the following aspects. Data communication between a processor and a memory is generally effected via a bus. In order to accomplish said communication, the bus should have a certain pass band in terms of number of bits per unit of time. The speed with which the processor accepts and supplies data, respectively when data is read out of or written into the memory, is governed by the required pass band. For example, a processor which processes video data in real time requires a bus having a comparatively large pass band.
In principle, the pass band of a bus depends on two factors. First of all, the pass band depends on the electrical characteristics of the lines forming the bus. For example, if a line has a substantial capacitance, this line can only transfer a comparatively small number of bits per unit of time. Secondly, the pass band depends on the number of lines forming the bus. For example, if a line can transfer 1 Mbit per second at the most, a bus comprising 10 lines (width=10 bits) will have a pass band of 10 Mbits per second. A bus comprising 100 lines (width=100 bits) will have a pass band of 100 Mbits per second.
A customary scheme is to use a collective bus via which different processors can access a collective memory. The prior-art document describes an example of this. Since the collective bus connects different processors to the collective memory it will generally have a substantial length. This means that the lines of this bus will have comparatively high capacitances. Therefore, in order to obtain an adequate pass band, the bus should have a comparatively large size, particularly for high-speed uses, as for example, video processing. A large-size bus is generally expensive, particularly in integrated circuit implementations because the bus occupies a comparatively large surface area.
According to the invention, an arrangement of the type defined in the opening paragraph comprises:
private buses, a private bus enabling data communication exclusively between a processor and the collective memory; and
a memory interface for maintaining a substantially steady data stream via the private buses, the collective memory being accessed in bursts.
This enables the width of each private bus to be optimized: the width of a private bus is such that the pass band suffices exactly for the relevant processor. The pass bands of the private buses will be utilized effectively because the memory interface ensures that these buses convey substantially steady data streams. Moreover, since a private bus needs to connect only a single processor to the collective memory, the bus will be comparatively short. Consequently, one line of the bus can transfer a comparatively large number of bits per unit of time. As a result of all these factors it is achieved that in a large number of implementations the private buses together will occupy less surface area than a collective bus as used in the prior art. Thus, the invention enables implementations to be realized at comparatively low cost.